Recently, electronic devices such as servers and personal computers have been remarkably developed in terms of advancements in speed, performance, and the like, and accordingly semiconductor elements such as CPU (Central Processing Unit) used in the electronic devices have been progressively increased in size.
As a mounting technology for semiconductor elements, flip chip mounting is known in which a semiconductor element in the form of bare chip is directly mounted on a wiring board with a solder hump.
Additionally, to scale up the fine electrode arrangement of semiconductor elements to the electrode arrangement of a wiring board, there is also a mounting method in a BGA (Ball Grid Array) approach in which a semiconductor package having a semiconductor element placed on an interposer is fabricated and mounted on a wiring board with a solder bump interposed therebetween. The semiconductor package for BGA approach is also called a BGA semiconductor package.
FIGS. 1A and 1B are cross-sectional views of a BGA semiconductor package 5 in the course of the mounting thereof on a wiring board 1.
As illustrated in FIG. 1A, the wiring board 1 has first electrode pads 2 on one main surface thereof. A solder paste 4 is printed in advance on the first electrode pads 2 by screen printing.
On the other hand, the semiconductor package 5 includes second electrode pads 6 on a main surface thereof at positions facing the first electrode pads 2. Further, solder bumps 7 are bonded to the upper surfaces of the second electrode pads 6.
Then, while the solder bumps 7 are in contact with the solder paste 4, these are reflowed by heating. Thereby, the semiconductor package 5 is mounted on the wiring board 1 as illustrated in FIG. 1B. The surface tension of the solder and the own weight of the semiconductor package 5 determine the shape of the solder bumps 7 after the reflowing, which is normally a drum-like shape bulging at the center as illustrated.
Meanwhile, the semiconductor package 5 and wiring board 1 have different thermal expansion coefficients because of the difference in materials. Accordingly, as the semiconductor package 5 generates heat, stress is applied on the solder bumps 7 due to the difference in thermal expansion coefficient. The stress concentrates on portions of the solder bumps 7 where the diameter is the smallest, in other words, around bonded portions A between the electrode pads 2, 6 and the solder bumps 7.
As the power supply of the semiconductor package 5 is turned on and off repeatedly, the stress is repeatedly applied to the solder bumps 7 in the bonded portions A. Thus, metal fatigue gradually progresses at the solder bumps 7. Eventually, a crack is generated in the solder bumps 7, and the bonded portions A may be fractured.
Patent Literature 1: Japanese Laid-open Patent Publication No. 05-114627
Patent Literature 2: International Publication Pamphlet No. WO 08/114434
Patent Literature 3: Japanese Laid-open Patent Publication No. 2001-118876
Patent Literature 4: Japanese Laid-open Patent Publication No. 08-236898
Patent Literature 5: Japanese National. Publication of International Patent Application No. 2005-510618
Non-patent Literature 1: Morita, Hayashi, Nakanishi, and Yoneda, “High Acceleration Test of Lead-free Solder”, 23rd Spring Lecture Meeting of Japan Institute of Electronics Packaging